1. Technical Field
The present invention relates generally to motion estimation technology and, more particularly, to motion estimation technology that, in order to process various block sizes using only minimum hardware in a parallel processing manner, classifies block sizes into three groups and then performs the parallel processing of each of the groups using common hardware.
2. Description of the Related Art
The ISO/IEC Moving Picture Experts Group (MPEG) and the ITU-T Video Coding Experts Group (VCEG), which developed the H.264/AVC standard, established the Joint Collaborative Team on Video Coding (JCT-VC). The JCT-VC is currently developing the High Efficiency Video Coding (HEVC) standard, which is a next-generation multimedia moving image compression standard. The HEVC standard is being developed with the principal technical aim of the achievement of the high compression ratio of the H.264 standard, and further with the ultimate aim of the implementation of a general-purpose moving image coding technology that can be used in almost all transmission media, such as storage media, the Internet and satellite broadcasting, and various moving image resolution environments.
When a System on Chip (SoC) based the HEVC standard, which is a multimedia moving image compression standard, is implemented, complexity increases in proportion to an increase in resolution. In particular, since a motion estimation block has the highest computational load among HEVC component blocks and the HEVC standard supports motion estimation for various-sized blocks, it has become a very important issue to more efficiently implement a motion estimation block.
Korean Patent Application Publication No. 2009-0079286 discloses a technology that, in order to perform pixel-based matching sequentially from the least frequent pixel in a current macroblock, obtains the partial sum of absolute differences (SAD) for each preset number of pixels of a candidate macro-block and then determines whether to early determinate the corresponding candidate macroblock by comparing the partial SAD with the minimum SAD.
However, Korean Patent Application Publication No. 2009-0079286 is not directed to a technology that supports all 12 block sizes, that is, 64×64, 64×32, 32×64, 32×32, 32×16, 16×32, 16×16, 16×8, 8×16, 8×8, 4×8 and 8×4 block sizes, supported in the HEVC standard, and is directed to a technology that is not related to parallel processing for various block sizes.
As a result, there is an urgent need for a new motion estimation technology that is capable of supporting all larger coding units (LCUs) suitable for HEVC-based motion estimation and performing appropriate parallel processing.